This invention relates generally to the assembly, interconnection and packaging of electronic devices. The invention more particularly relates to the electrical relocation of device top pads to the bottom of a device, as well as to the placement of devices, particularly arrays of devices, in precise locations. The invention is particularly useful in the fabrication of arrays of devices, such as imaging (viewing) or display devices, which are closely adjacent to each other and which must have precise alignment.
Many array structures such as solid state television image sensor arrays, infrared sensor arrays, x-ray imaging arrays, 3D holography and other display arrays, as well as other microelectronic and micromechanical devices, such as micro mirrors, require precision placement of individual devices or die to create an image free of artifacts which can be induced by component misalignment. Many of these devices require, in addition to accurate placement in an X-Y axis plane, accurate placement with reference to a Z directional axis, particularly in a focal plane array. Moreover, many die need to be less than 4 mils (0.004 inch) apart to avoid blank rows between the die which create voids in the generated image similar to netting projected onto a screen.
Related to the subject invention is a technology known as High Density Interconnect (HDI). Very briefly, and as disclosed in Eichelberger et al. U.S. Pat. No. 4,783,695, for example, an HDI structure employs a substrate on which various die and other components are placed and adhered in approximate desired locations, usually within a cavity. A multi-layer interconnect overcoat structure is then built up to electrically interconnect the components into an actual functioning system. As disclosed in aforementioned U.S. Pat. No. 4,783,695, the top surface is not necessarily planar, since the die cavities and die thicknesses vary, which causes a topology issue, particularly where components are mounted on top as disclosed in Wojnarowski et al. U.S. Pat. No. 5,200,810.
To begin the HDI overcoat structure, a polyimide dielectric film is laminated across the top of the die and other devices. The actual as-placed locations of the various components and contact pads thereon are determined, and via holes are adaptively laser drilled through the polyimide dielectric film in alignment with the contact pads on the electronic components. Thus, any misalignment of the individual electronic components and their contact pads on a surface, and in particular a variable surface (including a PCB (printed circuit board) as well as an HDI structure), is compensated for by an adaptive laser lithography system as disclosed in Eichelberger et al. U.S. Pat. No. 4,835,704. It may be noted that the adaptive lithography process accommodates initially poorly-placed die, but does not actually place or fix an initially poorly-placed die in a correct X-Y-Z axis position. The positions of the electrical connection pads are externally compensated for to allow die functionality.
Further details of the HDI embedded chip process are disclosed in Eichelberger et al. U.S. Pat. Nos. 4,933,042 and 5,094,709; Fillion et al. U.S. Pat. Nos. 5,353,498 and 5,497,033; and Wojnarowski et al. U.S. Pat. No. 5,546,654, for example.
The HDI process leads to an approximation of Wafer Scale Integration (WSI). Thus, die are placed in close proximity to each other to create a tile-like structure, and are interconnected to form an HDI module. Conventional HDI design rules and strategy require a minimum spacing between die, at least for adaptive lithography purposes, as well as for interconnection purposes in general, especially in the case of display or imaging (viewing) die where interconnections cannot cross the active area on top of the die and accordingly are limited to die edge regions and spaces between the die. This limits the maximum tile density that can be achieved.
State of the art solid state display applications, such as those that are desired to be used in 3D holography, as well as certain imaging (viewing) applications, include a die-to-die spacing of display or viewing die of less than 4 mils (0.004 inch), closer than the conventional HDI design rules allow, and which also leaves no room for die I/O and power connections. When conventional HDI technology is employed, a visible mesh grid is formed on a display screen, due to the relatively large spaces between die.
Additionally, conventional HDI technology employs an overlay technology that blocks a video sensor due to the filtering effect of the polymer overlay and adhesive. Removal of the overlay would include extensive large area ablation to selectively remove all of the polymer overlay material from the active areas. Some of these die, such as die made of InSb, HgCdTe and GaAs, are very sensitive to high temperatures and top surface damage which can result from laser ablation. When die are damaged due to large area ablation, the entire HDI overcoat structure must be removed to fix the damaged die. Additionally, many IR sensor die are very temperature-sensitive and cannot be subjected to processing temperatures greater than 100.degree. C. The need to avoid blocking the active area of a video sensor die also greatly limits the area available for interconnect wiring to top die connection pads.
The HDI process in general produces structures that are not flat on top due to die cavity and die thickness variations, resulting in height variations of at least .+-.0.5 mil to .+-.1.0 mil. However, disclosed in aforementioned U.S. Pat. Nos. 5,353,498 and 5,497,033 is a method which provides a flat surface across the tops of several die. The die top surfaces are placed flat against a polymer stretched film (which may be removable), and then a polymeric molding material is employed to encapsulate all die surfaces except the tops. While the method of aforementioned U.S. Pat. Nos. 5,353,498 and 5,497,033 potentially can provide a die array sufficiently flat for display and imaging applications, interconnections on the die top surfaces preclude a sufficiently close die-to-die placement for many display and imaging applications.
In addition to close spacing between die, accurate X-Y-Z axis alignment is important for imaging and displaying devices. Placing die, and other small device structures by any means gives rise to the question of tolerance variations and shifts, due to die-attach materials, cooling method and stresses, positioning of pads that hold die-attach materials, and movement induced by placement machine tooling. Even when die can accurately be initially placed, conventional attachment techniques move die from their initial placement. Die attach adhesives have surface tensions which cause die movement. Solvent drying cycles, curing mechanisms, solder or braze differential cooling stresses, all move the die from initial placement. Thus, it is well known that die can be placed with much more accuracy on sticky tape verses placing them by employing die attach adhesives.
Even when a device is correctly initially positioned in the X-Y axis plane, subsequent processing steps, such as employing a flat plate to achieve uniform placement with reference to the Z axis, which is a particular requirement in holography, and other optical arrays, as well as pressure lamination in general, disturb positioning in the plane of the X-Y axis. (Pressure lamination is used extensively in HDI processing.)
It is known that the principle of solder surface tension can be employed to align devices to desired positions over accurately-placed solder-wettable pads on a substrate, to some extent. Examples are disclosed in Napp et al. U.S. Pat. No. 4,836,435, and Braun et al. U.S. Pat. No. 5,118,027. However, bent leads and improperly positioned pads give rise to alignments which are not compensated for. In one technique known as Controlled Collapsed Chip Connection (C-4), solder-bumped die self align or snap-to-grid. These die have in excess of four hundred die pads with small solder bumps approximately 15 mils in diameter on the die. DGA (Die Grid Array Technology) uses the basic C-4 surface tension principle as well. This is widely used in flip-chip technology.
A method which combines die alignment by solder surface tension with planarization is disclosed in Paik et al. U.S. Pat. No. 5,352,629. The die in Paik et al. have their electrical connections on the die top surfaces, and are not sufficiently close together for many imaging and display applications.